Current digital receivers typically include a clock recovery circuit, a sample/hold circuit, and a comparator. An input signal having a pulse train is received and processed by the digital receiver to extract therefrom a data stream. Briefly, the clock recovery circuit recovers a clock from the input signal. The sample/hold circuit uses the recovered clock to sample the input pulse train and produce a steady signal level for processing by the comparator. The comparator compares the analog value of the sampled signal to a threshold value to determine the sample value, which may be further processed by demodulators and the like. This process is repeated for each clock cycle.
Operation of current digital receivers may be degraded in the presence of an input signal experiencing timing jitter. This is because the timing jitter causes the clock recovery circuit to select clock events that may be inaccurate, which in turn causes the data slicing level used by the comparator to be inaccurate, resulting in a bit errors that may or may not be correctable. Moreover, several bit periods are usually necessary for a recovered clock to be stable. Thus, due to clock recovery errors and/or the time necessary to establish a stable clock, the recovery of a burst mode digital transmission signal is difficult.